The present invention relates to a receiver for use with CDMA (code division multiple access) communication.
Direct sequence code division multiple access (DS-CDMA) is a technique for digital communications used particularly in cellular mobile communications. In this technique, a data signal is combined with a spreading waveform in the form of a pseudo random noise code (PN) to form a coded signal for transmission. The code has a frequency (the chip rate) which is a multiple of the frequency (the bit or symbol rate) of the data signal, so that an effect of combination of the data signal and spreading waveform is that the bit period is divided into smaller chip periods.
At the receiver, the processed signal is combined with the same spreading waveform to extract the data signal. The technique provides a high data capacity by spreading signal energy over a wide bandwidth to increase bandwidth utilization and reduce the effects of narrow band interference.
DS-CDMA requires that the spreading waveforms generated by transmitter and receiver are synchronized. If these two waveforms are out of synchronization by as little as one chip period, reliable communication cannot be achieved. The problem of synchronization is exacerbated by multipath effects, since the wireless channel from base station to mobile station is composed of several paths of different time delays, which vary due to the movement of the mobile station or Doppler shift effects.
A searcher formed by parallel correlators or matched filters is used to deal with rapid path changes caused principally by movement, while a plurality of Delay Locked Loops (DLL) are used to deal with slight changes in the phase of the spreading waveform caused principally by basic synchronization clock errors between transmitter and receiver or Doppler shift. Each path will have a corresponding portion of the receiver apparatus termed a "finger" including a DLL which keeps close track of phase fluctuations of the received signal from that path and adjusts its respective locally generated spreading waveform to follow the fluctuations.
DS-CDMA systems need to use an analogue to digital converter to sample and thus recover the received signal. In current systems, the converter includes a clock having a sampling rate of eight times the chip rate (CHIP8CLK). Each DLL uses this clock as a basis to adjust and align the phase of its locally generated spreading waveform. The smallest step of advance or retardation of the DLL's spreading waveform is thus 1/8 of the chip duration (Tc). Therefore, if the DLL works under perfect control, the timing error of each finger in tracking between the incoming and locally generated spreading waveforms is less than 1/16 Tc and the bit error rate (BER) performance degradation due to this error is negligible. However, if the sampling rate of the clock is reduced, performance degradation will increase to the point where reliable communication cannot be achieved.
In order to obtain higher capacity and support multimedia applications, systems using wide band code division multiple access (WCDMA) have been proposed. Such systems use a relatively wider band than the systems discussed above. However, operating in a wide band environment requires a corresponding increase in chip rate. This in turn requires a correspondingly faster sampling clock, which considerably increases cost and power consumption, since several internal modules operate under control of the clock.
It is an object of the invention to provide signal processing apparatus which alleviates this problem.